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Espressif Systems /ESP32-P4 /I3C_MST /PRESENT_STATE0

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Interpret as PRESENT_STATE0

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (SDA_LVL)SDA_LVL 0 (SCL_LVL)SCL_LVL 0 (BUS_BUSY)BUS_BUSY 0 (BUS_FREE)BUS_FREE 0CMD_TID0SCL_GEN_FSM_STATE 0IBI_EV_HANDLE_FSM_STATE 0I2C_MODE_FSM_STATE 0SDR_MODE_FSM_STATE 0DAA_MODE_FSM_STATE 0MAIN_FSM_STATE

Description

NA

Fields

SDA_LVL

This bit is used to check the SCL line level to recover from error and for debugging. This bit reflects the value of synchronized scl_in_a.
SCL_LVL

This bit is used to check the SDA line level to recover from error and for debugging. This bit reflects the value of synchronized sda_in_a.
BUS_BUSY

NA
BUS_FREE

NA
CMD_TID

NA
SCL_GEN_FSM_STATE

NA
IBI_EV_HANDLE_FSM_STATE

NA
I2C_MODE_FSM_STATE

NA
SDR_MODE_FSM_STATE

NA
DAA_MODE_FSM_STATE

Reflects whether the Master Controller is in IDLE or not. This bit will be set when all the buffer(Command, Response, IBI, Transmit, Receive) are empty along with the Master State machine is in idle state. 0X0: not in idle 0x1: in idle
MAIN_FSM_STATE

NA

Links

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Register License

Copyright 2024 Espressif Systems (Shanghai) PTE LTD

Licensed under the Apache License, Version 2.0 (the “License”); you may not use this file except in compliance with the License. You may obtain a copy of the License at

http://www.apache.org/licenses/LICENSE-2.0

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data